In the MEMS and micro-electronic fields there is frequently a need for bonding wafers together for the purpose of encapsulating structures in vacuum cavities or in cavities with controlled atmosphere. Such structures may have to be operable during very long times, most often tens of years. It can also be desirable to provide electrical connection between wafers via the sealing.
It is of course absolutely necessary that the joints that holds/bonds the wafers together and that provides the actual sealing of said cavities will provide good enough sealing that will not deteriorate over time.
There is also a strive towards more cost effective wafer-level packaging, rather than the prior art individual chip packaging.
There are several prior art methods that have been successfully used over the last ten years or so for packaging, i.a. glass frit bonding (see e.g. U.S. Pat. No. 5,604,160, Motorola), direct Si—Si fusion bonding, anodic glass bonding, eutectic bonding, soldering, just to mention some.
Whenever possible (i.e. flat substrates, and substrates without metal and unlimited thermal budget), fusion bonding is the most attractive bonding method for creating sealed structures, since it allows both silicon via integration, and monolithically integrated components, e.g. a polysilicon structure, an example of which is disclosed in WO 2008/091221 (Silex Microsystems).
In fusion bonding one can use various combinations of material (high purity, long term stable) in the substrates to be bonded together, e.g. Si—Si, Si—SiO or SiO—SiO, with full Si—Si bond.
The advantages of fusion bonding are the following:
The bond exhibits high bond strength and the sealing obtained is tight. A bond width area for tight seals of <100 μm is attainable. There are no foreign materials involved that could cause problems with mechanical strength e.g. due to different thermal expansion between sealing material and substrate.
Fusion bonding is preferably done at the beginning of a process flow, before the wafers have been structured with topography.
It enables pre-processing with unrestricted thermal budget (contact doping and anneal for SOI based Sil-Vias possible) and also wet processing is possible.
It is attractive for electrostatic/capacitive systems with silicon via integration in the CAP. This is particularly useful in for example gyro and accelerometer applications, that can be manufactured in accordance with methods defined and described in applicants own WO 2004/084300 and WO 2008/091221.
Among disadvantages the following can be mentioned:
The resistance in Si—Si bonding could become too high if low ohmic interconnections are required, and Si—SiO— and SiO—SiO-bonds do not give electrical interconnection (SiO=insulator).
Certain versions of fusion bonding (>1000° C. anneal) are not CMOS compatible, but others have demonstrated that low temp fusion bond is possible by plasma assisted methods, but here is still ongoing discussions how tight the seal one gets really is. There is still a risk for leakage.
However, the largest disadvantage by far of fusion bonding is its sensitivity to topography. Fusion bonding requires ultra flat surfaces making integrating vias of silicon or metal vias made prior to bonding (“via-first” approach”) difficult if not impossible.
Also, bonding wafers together to form a “sealing” bond if one of the wafers is metallised (i.e. exhibiting topography) CMOS wafer requiring electrical connection between the wafer is not possible.
Other methods have been attempted but have not been so successful, such as thermo compression bonding (TC bonding) and eutectic bonding. The last two methods have been investigated in two doctoral theses, namely “LOW TEMPERATURE WAFER LEVEL VACUUM PACKAGING USING AU-SI EUTECTIC BONDING AND LOCALIZED HEATING” by Jay S. Mitchell (The University of Michigan, 2008), and “FABRICATION AND CHARACTERIZATION OF WAFER LEVEL GOLD THERMO COMPRESSION BONDING” by C. H. Tsau, (Massachusetts Institute of Technology 2003), both of which are incorporated herein in their entirety by reference.
WO 03/068669 (Silex Microsystems) describes MEMS devices based on eutectic and solder wafer level bonding methods.
In U.S. Pat. No. 7,183,622 (Intel) there is disclosed an apparatus including a first substrate, one or more microelectromechanical systems (MEMS) coupled to the first substrate, a second substrate coupled with the first substrate, and one or more passive components coupled to the second substrate. A method may include aligning a first substrate having one or more MEMS coupled thereto and a second substrate having one or more passive components coupled thereto, and coupling the aligned substrates.
In U.S. Pat. No. 7,442,570 (InvenSense) there is disclosed a method of bonding of germanium to aluminum between two substrates to create a robust electrical and mechanical contact is disclosed. The bond has the attributes: (1) it can form a hermetic seal; (2) it can be used to create an electrically conductive path between two substrates; (3) it can be patterned so that this conduction path is localized.
All of these methods have their advantages and disadvantages.
One problem is that deviations from flatness on substrates to be joined by bonding, i.e. substrates exhibiting a topography across their surface, may cause weak points in the bond that eventually can give rise to leakage into or out from the sealed off cavity. Even worse, the sealing may be deficient from the start, i.e. there was not a complete sealing of the cavity already during manufacture, which means that the yield will be lowered.
Another problem is that gold, which is the most commonly used sealing medium can have a tendency to “drift away” by diffusion, i.e. the sealing joint may become depleted of material, which can give rise to the above mentioned leakage problem.